1. Field of the Invention
This invention relates to data processing.
2. Description of the Prior Art
Some electronic data processing devices employ a processing core which can operate in accordance with a number of possible operating modes or states. In a simple example, the processing core may operate in either an "internal operation" mode or a "memory access" mode, depending on the particular processing task which has to be performed at any time.
It has been proposed to use a synchronous state machine to control the transition between the various operating states of such a processing core. Synchronous state machines are logic circuits which generally comprise both combinational logic and clocked registers, with a degree of feedback so that signals generated in response to a clocking pulse are passed back as inputs to a part of the circuit for use at the next clocking pulse. These circuits have a number of permitted output "states", represented by the logic levels of one or more output signals, and various permitted transitions between the output states. Because of the use of feedback, the circuit will move in a permitted transition from one state to another in response to particular sets of input signals. The transitions between states all take place in response to the clocking signal; for this reason such circuits are referred to as synchronous state machines.
In the simple example described above, a state machine may control synchronous transitions between the two possible operating states of the processing core. This can be achieved by supplying various inputs to the state machine representing the current and next tasks to be performed by the core and other current operating features of the data processing device. The output of the state machine is then connected as a control input to the processing core.
For example, when a memory access is required, the state machine would generate an output state controlling the core to assume the "memory access" mode. When the required memory address has been accessed, the state machine's output might revert back to an output controlling the core to assume the "internal operation" mode.